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CAT24C256 256 kb I2C CMOS Serial EEPROM
Description
The CAT24C256 is a 256 kb Serial CMOS EEPROM, internally organized as 32,768 words of 8 bits each. It features a 64-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). External address pins make it possible to address up to eight CAT24C256 devices on the same bus.
Features
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SOIC-8 W SUFFIX CASE 751BD
TDFN-8 ZD2 SUFFIX CASE 511AM
SOIC-8 X SUFFIX CASE 751BE
* * * * * * * * * * *
Supports Standard and Fast I2C Protocol 1.8 V to 5.5 V Supply Voltage Range 64-Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range PDIP, SOIC, TSSOP and TDFN 8-lead Packages This Device is Pb-Free, Halogen Free/BFR Free, and RoHS Compliant
VCC
PDIP-8 L SUFFIX CASE 646AA
TSSOP-8 Y SUFFIX CASE 948AL
PIN CONFIGURATION
A0 A1 A2 VSS 1 VCC WP SCL SDA
PDIP (L), SOIC (W, X), TSSOP (Y), TDFN (ZD2) For the location of Pin 1, please consult the corresponding package drawing.
SCL CAT24C256 SDA
A2, A1, A0 WP
PIN FUNCTION
Pin Name A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Serial Data Serial Clock Write Protect Power Supply Ground
VSS
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
November, 2009 - Rev. 9
1
Publication Order Number: CAT24C256/D
CAT24C256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Ratings -65 to +150 -0.5 to +6.5 Units C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program/Erase Cycles Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = -40C to +125C, unless otherwise specified.)
Symbol ICCR ICC ISB IL VIL VIH VOL1 VOL2 Parameter Read Current Write Current Standby Current Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC Pin at GND or VCC TA = -40C to +85C TA = -40C to +125C I/O Pin Leakage TA = -40C to +85C TA = -40C to +125C Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA -0.5 VCC x 0.7 Min Max 1 3 1 2 1 2 VCC x 0.3 VCC + 0.5 0.4 0.2 V V V V mA Units mA mA mA
Table 4. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = -40C to +125C, unless otherwise specified.) Symbol CIN (Note 4) CIN (Note 4) IWP (Note 5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current (Product Revision C and higher) VIN = 0 V VIN = 0 V VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.3 V VIN < VIH, VCC = 1.8 V VIN > VIH Conditions Max 8 6 130 120 80 1 Units pF pF mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source. The variable WP input impedance is available only for Die Rev. C and higher.
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CAT24C256
Table 5. A.C. CHARACTERISTICS (Note 6) (VCC = 1.8 V to 5.5 V, TA = -40C to +125C, unless otherwise specified.)
Standard VCC = 1.8 V - 5.5 V Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR (Note 7) tF (Note 7) tSU:STO tBUF tAA tDH Ti (Note 7) tSU:WP tHD:WP tWR tPU (Notes 7, 8) 6. 7. 8. 9. Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode 0 2.5 5 1 100 100 0 2.5 5 1 0.1 4 4.7 3.5 100 100 0 1 5 1 4 4.7 4 4.7 0 250 1,000 300 0.6 1.3 0.9 50 100 Min Max 100 0.6 1.3 0.6 0.6 0 100 300 300 0.25 0.5 0.50 Fast VCC = 1.8 V - 5.5 V Min Max 400 0.25 0.55 0.25 0.25 0 50 100 100 Fast-Plus (Note 9) VCC = 2.5 V - 5.5 V TA = -405C to +855C Min Max 1,000 Units kHz ms ms ms ms ms ns ns ns ms ms ms ns ns ms ms ms ms
Test conditions according to "A.C. Test Conditions" table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Fast-Plus (1 MHz) speed class available for product revision "D", identified by letter "D" marked on top of the package.
Table 6. A.C. TEST CONDITIONS
Input Levels Input Rise and Fall Times Input Reference Levels Output Reference Levels Output Load 0.2 x VCC to 0.8 x VCC 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source: IL = 3 mA (VCC 2.5 V); IL = 1 mA (VCC < 2.5 V); CL = 100 pF
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CAT24C256
Power-On Reset (POR) The CAT24C256 Die Rev. C incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against brown-out failure, following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock signal generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins accept the device address. These pins have on-chip pull-down resistors. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on-chip pull-down resistor. Functional Description The CAT24C256 supports the Inter-Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The CAT24C256 acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Up to 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2.
I2C Bus Protocol
device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 2).
START
The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a `wake-up' call to all receivers. Absent a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP starts the internal Write cycle (when following a Write command) or sends the Slave into standby mode (when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address are set to 1010, for normal Read/Write operations (Figure 3). The next 3 bits, A2, A1 and A0, select one of 8 possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed.
Acknowledge
The I2C bus consists of two `wires', SCL and SDA. The two wires are connected to the VCC supply via pull-up resistors. Master and Slave devices connect to the 2-wire bus via their respective SCL and SDA pins. The transmitting
After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. If the Master acknowledges the data, then the Slave continues transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by sending a STOP to the Slave. Bus timing is illustrated in Figure 5.
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CAT24C256
SCL
SDA START CONDITION STOP CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER 1 8 9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM RECEIVER START ACK DELAY ( tAA) ACK SETUP ( tSU:DAT)
Figure 4. Acknowledge Timing
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:STA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
tDH
tBUF
Figure 5. Bus Timing
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CAT24C256
WRITE OPERATIONS
Byte Write
(within the selected page). The internal Write cycle starts immediately following the STOP.
Acknowledge Polling
In Byte Write mode the Master sends a START, followed by Slave address, two byte address and data to be written (Figure 6). The Slave acknowledges all 4 bytes, and the Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 7). During internal Write, the Slave will not acknowledge any Read or Write request from the Master.
Page Write
Acknowledge polling can be used to determine if the CAT24C256 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a `Selective Read' command (see READ OPERATIONS). The CAT24C256 will not acknowledge the Slave address, as long as internal Write is in progress.
Hardware Write Protection
The CAT24C256 contains 32,768 bytes of data, arranged in 512 pages of 64 bytes each. A two byte address word, following the Slave address, points to the first byte to be written. The most significant bit of the address word is `don't care', the next 9 bits identify the page and the last 6 bits identify the byte within the page. Up to 64 bytes can be written in one Write cycle (Figure 8). The internal byte address counter is automatically incremented after each data byte is loaded. If the Master transmits more than 64 data bytes, then earlier bytes will be overwritten by later bytes in a `wrap-around' fashion
With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the CAT24C256. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the CAT24C256 will not acknowledge the data byte and the Write request will be rejected.
Delivery State
The CAT24C256 is shipped erased, i.e., all bytes are FFh.
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CAT24C256
S T BUS ACTIVITY: A MASTER R T SDA LINE S A C K S T O P P A C K A C K A C K
SLAVE ADDRESS *
BYTE ADDRESS A7 - A0 A15 - A8
DATA
* = Don't Care Bit
Figure 6. Byte Write Timing
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 7. Write Cycle Timing
S BUS T ACTIVITY: A MASTER R T SDA LINE S
SLAVE ADDRESS * A C K
BYTE ADDRESS A15 - A8 A7 - A0
DATA
DATA n
DATA n+63
S T O P P
* = Don't Care Bit
A C K
A C K
A C K
A C K
A C K
A C K
Figure 8. Page Write Timing
ADDRESS BYTE 1 SCL 8 9 1
DATA BYTE 8
SDA
a7
a0 tSU:WP
d7
d0
WP tHD:WP
Figure 9. WP Timing
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CAT24C256
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT24C256 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If that `previous' byte was the last byte in memory, then the address counter will point to the 1st memory byte, etc. When, following a START, the CAT24C256 is presented with a Slave address containing a `1' in the R/W bit position (Figure 10), it will acknowledge (ACK) in the 9th clock cycle, and will then transmit data being pointed at by the internal address counter. The Master can stop further transmission by issuing a NoACK, followed by a STOP condition.
Selective Read
The address counter can be initialized by performing a `dummy' Write operation (Figure 11). Here the START is followed by the Slave address (with the R/W bit set to `0') and the desired two byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the `Immediate Address Read' sequence, as described earlier.
Sequential Read
The Read operation can also be started at an address different from the one stored in the internal address counter.
S T BUS ACTIVITY: A MASTER R T SDA LINE S
If the Master acknowledges the 1st data byte transmitted by the CAT24C256, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Figure 12). If the end of memory is reached during sequential Read, then the address counter will `wrap-around' to the beginning of memory, etc. Sequential Read works with either `Immediate Address Read' or `Selective Read', the only difference being the starting byte address.
S T O P P A C K DATA N O A C K
SLAVE ADDRESS
SCL
8
9
SDA
8th Bit DATA OUT NO ACK STOP
Figure 10. Immediate Address Read Timing
S T BUS ACTIVITY: A MASTER R T SDA LINE S * = Don't Care Bit A C K S T A R T S A C K A C K A C K N O A C K S T O P P A C K A C K A C K A C K N O A C K S T O P P
SLAVE ADDRESS *
BYTE ADDRESS A15 - A8 A7 - A0
SLAVE ADDRESS
DATA
Figure 11. Selective Read Timing
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
Figure 12. Sequential Read Timing
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CAT24C256
PACKAGE DIMENSIONS
PDIP-8, 300 mils CASE 646AA-01 ISSUE A
SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33
TOP VIEW E
A
A2
A1 b2 L c
e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001.
b
eB
END VIEW
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CAT24C256
PACKAGE DIMENSIONS
SOIC 8, 150 mils CASE 751BD-01 ISSUE O
SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00
0
8
D
h
A1
A
c e SIDE VIEW b L END VIEW
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.
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CAT24C256
PACKAGE DIMENSIONS
TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O
b
SYMBOL
A A1 A2 b E1 E c D E E1 e L L1
MIN
0.05 0.80 0.19 0.09 2.90 6.30 4.30
NOM
MAX
1.20 0.15
0.90
1.05 0.30 0.20
3.00 6.40 4.40 0.65 BSC 1.00 REF
3.10 6.50 4.50
0.50
0.60
0.75
e
0
8
TOP VIEW D
A2
A
q1
c
A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.
L1 END VIEW
L
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CAT24C256
PACKAGE DIMENSIONS
TDFN8, 3x4.9 CASE 511AM-01 ISSUE A
D A
DETAIL A
DAP SIZE 2.6 x 3.3mm
E
E2 PIN #1 IDENTIFICATION
A1 PIN #1 IDENTIFICATION TOP VIEW SIDE VIEW D2 BOTTOM VIEW
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45
NOM 0.75 0.02 0.55 0.20 REF
MAX 0.80 0.05 0.65 A1 FRONT VIEW b A3 A A2
0.25 2.90 0.90 4.80 0.90 0.50
0.30 3.00 1.00 4.90 1.00 0.65 TYP 0.60
0.35 3.10 1.10 5.00 1.10 0.70 e
L
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229.
DETAIL A
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CAT24C256
PACKAGE DIMENSIONS
SOIC-8, 208 mils CASE 751BE-01 ISSUE O
SYMBOL A A1 b c E1 E D E E1 e L
MIN
NOM
MAX 2.03
0.05 0.36 0.19 5.13 7.75 5.13 1.27 BSC 0.51
0.25 0.48 0.25 5.33 8.26 5.38 0.76
PIN#1 IDENTIFICATION TOP VIEW
0
8
D
A
q
e
b
A1
L
c END VIEW
SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320.
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CAT24C256
Example of Ordering Information (Note 12)
Prefix CAT Device # 24C256 Suffix W I -G T3
Company ID (Optional) Product Number 24C256
Temperature Range I = Industrial (-40C to +85C) E = Extended (-40C to +125C)
Lead Finish G: NiPdAu Blank: Matte-Tin (Note 13) Tape & Reel (Note 17) T: Tape & Reel 2: 2,000 / Reel (Notes 13, 14) 3: 3,000 / Reel
Package L: PDIP W: SOIC, JEDEC X: SOIC, EIAJ (Note ) Y: TSSOP ZD2: TDFN (3 x 4.9 mm) (Note 14)
ORDERING INFORMATION
Orderable Part Numbers
CAT24C256LI-G CAT24C256WI-GT3 CAT24C256XI-T2 CAT24C256YI-GT3 CAT24C256ZD2IGT2* (Note 16) CAT24C256LE-G CAT24C256WE-GT3 CAT24C256XE-T2 CAT24C256YE-GT3 CAT24C256ZD2EGT2* (Note 16)
10. All packages are RoHS-compliant (Lead-free, Halogen-free). 11. The standard lead finish is NiPdAu. 12. The device used in the above example is a CAT24C256WI-GT3 (SOIC-JEDEC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 13. For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2,000 pcs/reel, i.e., CAT24C256XI-T2. 14. The TDFN 3 x 4.9 mm (ZD2) package is available in 2,000 pcs/reel, i.e., CAT24C256ZD2I-GT2. 15. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 16. Part number is not exactly the same as the "Example of Ordering Information" shown above. For part numbers marked with * there are NO hyphens in the orderable part numbers. 17. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CAT24C256/D

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